It is necessary to design, implement and test a circuit that implements a natural number addition: Digital Circuits Assignment, QUB, Ireland

For this assignment, it is necessary to design, implement and test a circuit that implements a natural number addition function with two outputs, S and C defined as:

• A, B, S(A, B) ∈ { x ∈ N 0 ≤ x < N .
• C(A, B) ∈ ₿
• N = 4

For the function, students should design, test, and analyze a transistor-level (or another suitable component) circuit to implement the computing function chosen, including:

• the discretized representation of the computing function and the impact on the final circuit;
• describe how the valid range of input and output voltages and how they map to the discretized representations;
• identify the maximum propagation paths through the transistor-level circuit and the number of logic elements or transistors connected to each other;
• through simulation or otherwise, identify the timing parameters of the circuit including the maximum delays, minimum hold times, etc.
• assess how the number of logic elements and transistors changes if the input ranges were to scale.